Presently a state-of-the-art DRAM comprises a silicon chip in whose central (array) area is disposed an array of memory cells that are arranged in rows and columns and in whose peripheral area is disposed the support circuitry for reading in and reading out binary digits (bits) stored in the memory cells. Generally at the present state of the art, each memory cell includes an N-channel metal-oxide-semiconductor field effect transistor (N-MOSFET) and the support circuitry includes both N-MOSFETs and P-channel metal-oxide-semiconductor field effect transistors (P-MOSFETs) which are commonly known as complementary metal-oxide semiconductor field effect transistors (C-MOSFETs). In most state-of-the-art DRAMs, both the array transistors and the support transistors use polycide (such as WSi.sub.X) gates that are formed as stacks that are essentially identical for all transistors. This approach is cost-effective since it permits all gates to be deposited and patterned simultaneously, ensuring ease and reduced cost of manufacture. Typically the stacks are sequential layers of n-type doped polysilicon, a polycide, and a silicon nitride cap. This however poses limitations on the DRAM performance, particularly with respect to the P-MOSFET in the support circuitry. This will become more serious in the future when enhanced performance of the support circuitry will be necessary to cope with the improved performance requirements that will then be needed.
Also, DRAM technology typically aims to reduce the cell size in the arrays to permit higher density and increased productivity. One of the most effective ways to reduce the array cell size is to use borderless contacts to the source/drain regions (the output of the transistor typically coupled to a bit line of the DRAM) of the transistors of the memory cell. This requires a relatively thick SiN cap on top of the electrically conducting portion of the gate stack. Such a cap, which is also needed in the support circuitry, adds difficulty to line width control during etching, which in turn makes difficult control of gate width, another important factor in device performance.
High performance logic circuits, on the other hand, typically are now manufactured with n-type and p-type doped polysilicon as part of the gate stack for N-MOSFETs and P-MOSFETs, respectively, which is generally described as a dual work-function stack. These are manufactured with so-called salicide (self-aligned suicide) processes that simultaneously dope the gate polysilicon as well as the silicon substrate to form the source and drain diffusion regions. The absence of the need of the SiN cap in this approach results in better line-width control. The disadvantage to this approach is the need for additional masks. This increases the process complexity as well as a reduction in the allowed thermal budget because of the large thermal diffusion constant of the p-type dopant (typically boron). This factor limits the use of the anneal steps generally used to reflow the customary borophospho-silicate glasses (BPSG) because of the high aspect ratio of the spaces between gates in the circuitry.